{ "commit": { "sha": "d9c0c4c01e753b213fe9e4d11d24523616c7fc09", "date": "2026-07-04T17:15:58+00:00", "subject": "hw: move USB-C for 8032SK (WIP)", "url": "https://github.com/DLehenbauer/econopet/commit/d9c0c4c01e753b213fe9e4d11d24523616c7fc09", "board": "hw/rev-b/mainboard/kicad/Mainboard.kicad_pcb" }, "project": { "title": "EconoPET mainboard (rev. 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353.6125, 189.04025 ], "b": [ 91.1125, 93.792, 353.6125, 189.04025 ] }, "size": { "a": [ 262.5, 95.24825 ], "b": [ 262.5, 95.24825 ] }, "perimeterMm": { "a": 567.876702307, "b": 566.784518151, "delta": -1.092184157 }, "areaMm2": { "a": 10128.883844019, "b": -7369.706308777, "delta": -17498.590152796 }, "changedLengthMm": { "removed": 19.643310882, "added": 18.453430892 } }, "stackup": { "changed": false, "added": [], "removed": [], "modified": [], "reordered": false, "thickness": null }, "warnings": [] }, "bomDiff": { "summary": { "added": 0, "removed": 1, "qtyChanged": 0, "valueChanged": 0, "footprintChanged": 0, "mpnChanged": 0, "dnpToggled": 0, "categoryChanged": 0, "total": 1, "unchanged": 307 }, "added": [], "removed": [ { "kind": "removed", "category": "SCH", "key": "vf:menu_hdr|pinheader_1x02_p2.54mm_vertical", "part": { "value": "MENU_HDR", "footprint": "Connector_PinHeader_2.54mm:PinHeader_1x02_P2.54mm_Vertical" }, "qtyFrom": 1, "refs": [ "J23" ] } ], "qtyChanged": [], "valueChanged": [], "footprintChanged": [], "mpnChanged": [], "dnpToggled": [], "categoryChanged": [], "byCategory": { "SCH": { "removed": 1 }, "PCB": {}, "BOARD_FEATURE": {} } }, "impacts": [ { "id": "8ff9e8f802b1d94a", "kind": "bom", "ref": "J23", "category": "SCH", "metric": "qty", "before": 1, "after": 0, "delta": -1, "severity": "info", "why": "SCH line MENU_HDR PinHeader_1x02_P2.54mm_Vertical: J23 removed (qty 1 -> 0).", "causes": [ "bomDiff.removed[J23]" ], "assumptionDependent": false }, { "id": "e57d9526affdb7d3", "kind": "cert", "scope": "board", "metric": "ul796.findings", "before": 177, "after": 2, "delta": -175, "severity": "info", "why": "UL 796 pre-check findings 177 -> 2; verdict \"outside the fab's UL-recognized construction\".", "causes": [ "layoutDiff.nets.changed[/MAGIC/MCU/GP25]", "layoutDiff.nets.changed[/MAGIC/MCU/USB/VBUS]", "layoutDiff.nets.changed[Net-(D11-A)]", "layoutDiff.nets.changed[Net-(J25-DAT1)]", "layoutDiff.nets.changed[Net-(J25-DAT2)]", "layoutDiff.outline" ], "assumptionDependent": true }, { "id": "88d02c84d992cf32", "kind": "impedance", "net": "/MAGIC/MCU/GP25", "layer": "B.Cu", "metric": "z0Ohm", "before": 93.58, "after": null, "delta": null, "severity": "info", "why": "/MAGIC/MCU/GP25: rerouted (4.023 mm new copper); no longer on B.Cu; vias 2 -> 0; +3 more - Z0 on B.Cu gone (was 93.58 ohm).", "causes": [ "layoutDiff.components.moved[R43]", "layoutDiff.nets.changed[/MAGIC/MCU/GP25]", "layoutDiff.outline" ], "assumptionDependent": true }, { "id": "ee6c07ff00fccdad", "kind": "impedance", "net": "/MAGIC/MCU/USB/VBUS", "layer": "B.Cu", "metric": "z0Ohm", "before": 48.72, "after": null, "delta": null, "severity": "info", "why": "/MAGIC/MCU/USB/VBUS: rerouted (17.09 mm new copper); no longer on B.Cu; F.Cu width 0.3125-1.6 -> 0.25-1.15 mm; +15 more - Z0 on B.Cu gone (was 48.72 ohm).", "causes": [ "layoutDiff.components.moved[C102]", "layoutDiff.components.moved[C103]", "layoutDiff.components.moved[D12]", "layoutDiff.components.moved[J26]", "layoutDiff.components.moved[R63]", "layoutDiff.components.moved[R64]", "layoutDiff.nets.changed[/MAGIC/MCU/USB/VBUS]", "layoutDiff.outline" ], "assumptionDependent": true }, { "id": "4c989deb00902c11", "kind": "impedance", "net": "/MAGIC/MCU/USB/VBUS", "layer": "F.Cu", "metric": "z0Ohm", "before": 60.5, "after": 81.52, "delta": 21.02, "severity": "info", "why": "/MAGIC/MCU/USB/VBUS: rerouted (17.09 mm new copper); no longer on B.Cu; F.Cu width 0.3125-1.6 -> 0.25-1.15 mm; +15 more - Z0 on F.Cu 60.5 ohm -> 81.52 ohm (+21.02), with no limit to judge against.", "causes": [ "layoutDiff.components.moved[C102]", "layoutDiff.components.moved[C103]", "layoutDiff.components.moved[D12]", "layoutDiff.components.moved[J26]", "layoutDiff.components.moved[R63]", "layoutDiff.components.moved[R64]", "layoutDiff.nets.changed[/MAGIC/MCU/USB/VBUS]", "layoutDiff.outline" ], "assumptionDependent": true }, { "id": "06e1017e336bba80", "kind": "impedance", "net": "Net-(D11-A)", "layer": "F.Cu", "metric": "z0Ohm", "before": 87, "after": null, "delta": null, "severity": "info", "why": "Net-(D11-A): rerouted (0 mm new copper); no longer on F.Cu; D11 moved 10.15 mm; +3 more - Z0 on F.Cu gone (was 87 ohm).", "causes": [ "layoutDiff.components.moved[D11]", "layoutDiff.components.moved[R43]", "layoutDiff.nets.changed[Net-(D11-A)]", "layoutDiff.outline" ], "assumptionDependent": true }, { "id": "1742ac42723dee47", "kind": "impedance", "net": "Net-(J25-DAT1)", "layer": "F.Cu", "metric": "z0Ohm", "before": 87, "after": 93.58, "delta": 6.58, "severity": "info", "why": "Net-(J25-DAT1): rerouted (4.633 mm new copper); F.Cu width 0.25 -> 0.2 mm; pads +RN16.4 -R62.2; +3 more - Z0 on F.Cu 87 ohm -> 93.58 ohm (+6.58), with no limit to judge against.", "causes": [ "layoutDiff.components.moved[R62]", "layoutDiff.components.moved[RN16]", "layoutDiff.nets.changed[Net-(J25-DAT1)]", "layoutDiff.outline" ], "assumptionDependent": true }, { "id": "19547e4f857a58fe", "kind": "impedance", "net": "Net-(J25-DAT2)", "layer": "F.Cu", "metric": "z0Ohm", "before": 87, "after": 93.58, "delta": 6.58, "severity": "info", "why": "Net-(J25-DAT2): rerouted (13.64 mm new copper); F.Cu width 0.25 -> 0.2 mm; pads +R62.2 -RN16.1; +3 more - Z0 on F.Cu 87 ohm -> 93.58 ohm (+6.58), with no limit to judge against.", "causes": [ "layoutDiff.components.moved[R62]", "layoutDiff.components.moved[RN16]", "layoutDiff.nets.changed[Net-(J25-DAT2)]", "layoutDiff.outline" ], "assumptionDependent": true } ], "summary": { "counts": { "high": 0, "medium": 0, "low": 0, "info": 8 }, "headline": "8 informational change(s), none against a limit; first: SCH line MENU_HDR PinHeader_1x02_P2.54mm_Vertical: J23 removed (qty 1 -> 0).", "markdown": "**8 informational change(s), none against a limit; first: SCH line MENU_HDR PinHeader_1x02_P2.54mm_Vertical: J23 removed (qty 1 -> 0).** Layout: components: 1 removed, 14 moved, 8 rotated; nets: 16 rerouted; the outline changed. BOM: 1 removed. Re-analysed on both revisions, for the changed nets and parts only: impedance, cert. Every electrical change is informational (improved, or no limit to judge against). Not run for missing inputs: cert.creepage, returnPath (see refused). Rows marked assumptionDependent rest on ledgered typical values." }, "analysed": { "ran": [ "impedance", "cert" ], "nets": [ "+3V3", "+5V", "/MAGIC/FPGA/SPI1_RX", "/MAGIC/FPGA/SPI1_TX", "/MAGIC/MCU/GP25", "/MAGIC/MCU/GP27", "/MAGIC/MCU/SD_~{CS}", "/MAGIC/MCU/USB/CC1", "/MAGIC/MCU/USB/CC2", "/MAGIC/MCU/USB/USB_D+", "/MAGIC/MCU/USB/USB_D-", "/MAGIC/MCU/USB/VBUS", "GND", "Net-(D11-A)", "Net-(J25-DAT1)", "Net-(J25-DAT2)", "unconnected-(J26-SBU1-PadA8)", "unconnected-(J26-SBU2-PadB8)" ], "rails": [] }, "assumptions": { "before": [ { "source": "default", "analysis": "impedance", "key": "mask.er", "value": 3.8, "citation": "LPI solder mask epsilon_r 3.8 (NativeCAD default)", "verified": false, "affects": [ "outer-layer traces" ] }, { "source": "default", "analysis": "cert", "key": "fab", "value": "jlcpcb", "citation": "fab profile jlcpcb (NativeCAD default)", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "ipc6012.drillPositionTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.innerRegistrationTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.outerRegistrationTolMm", "value": 0.05, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipcClass", "value": "2", "citation": "IPC-6012 Class 2 (dedicated service) - the general commercial default", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "motC", "value": 105, "citation": "requested MOT 105 C (FR-4 laminates' common UL RTI)", "verified": false, "affects": [], "unit": "C" }, { "source": "default", "analysis": "returnPath", "key": "erEff", "value": 4, "citation": "effective epsilon_r 4 for the stitching distance (NativeCAD default)", "verified": false, "affects": [] }, { "source": "derived", "analysis": "returnPath", "key": "planes", "value": [], "citation": "inner layer with >= 30 % pour cover of one net (outer: >= 80 % and no other net's traces); voids = holes >= 2 mm^2 in that net's pours, as bounding rectangles", "affects": [ "every finding" ] }, { "source": "default", "analysis": "returnPath", "key": "riseTimeNs", "value": 1, "citation": "edge rise time 1 ns, f_knee = 0.35 / t_r (Johnson & Graham)", "verified": true, "affects": [], "unit": "ns" } ], "after": [ { "source": "default", "analysis": "impedance", "key": "mask.er", "value": 3.8, "citation": "LPI solder mask epsilon_r 3.8 (NativeCAD default)", "verified": false, "affects": [ "outer-layer traces" ] }, { "source": "default", "analysis": "cert", "key": "fab", "value": "jlcpcb", "citation": "fab profile jlcpcb (NativeCAD default)", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "ipc6012.drillPositionTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.innerRegistrationTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.outerRegistrationTolMm", "value": 0.05, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipcClass", "value": "2", "citation": "IPC-6012 Class 2 (dedicated service) - the general commercial default", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "motC", "value": 105, "citation": "requested MOT 105 C (FR-4 laminates' common UL RTI)", "verified": false, "affects": [], "unit": "C" }, { "source": "default", "analysis": "returnPath", "key": "erEff", "value": 4, "citation": "effective epsilon_r 4 for the stitching distance (NativeCAD default)", "verified": false, "affects": [] }, { "source": "derived", "analysis": "returnPath", "key": "planes", "value": [], "citation": "inner layer with >= 30 % pour cover of one net (outer: >= 80 % and no other net's traces); voids = holes >= 2 mm^2 in that net's pours, as bounding rectangles", "affects": [ "every finding" ] }, { "source": "default", "analysis": "returnPath", "key": "riseTimeNs", "value": 1, "citation": "edge rise time 1 ns, f_knee = 0.35 / t_r (Johnson & Graham)", "verified": true, "affects": [], "unit": "ns" } ] }, "refused": { "before": [ { "analysis": "cert.creepage", "reasonCode": "pcb_analysis_needs_input", "needs": [ "cert.pairs[].a", "cert.pairs[].b", "cert.pairs[].workingVrms" ], "remedy": "creepage needs the net pairs and the working voltage between them; UL 796 and IPC-6012 ran without them", "requested": false }, { "analysis": "returnPath", "reasonCode": "pcb_analysis_needs_input", "needs": [ "a reference plane (a poured copper layer)" ], "remedy": "no layer of this board is a plane, so there is no return path to check", "requested": false } ], "after": [ { "analysis": "cert.creepage", "reasonCode": "pcb_analysis_needs_input", "needs": [ "cert.pairs[].a", "cert.pairs[].b", "cert.pairs[].workingVrms" ], "remedy": "creepage needs the net pairs and the working voltage between them; UL 796 and IPC-6012 ran without them", "requested": false }, { "analysis": "returnPath", "reasonCode": "pcb_analysis_needs_input", "needs": [ "a reference plane (a poured copper layer)" ], "remedy": "no layer of this board is a plane, so there is no return path to check", "requested": false } ] } } }