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{ "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 1, "b": 1, "delta": 0, "drills": { "a": { "0.3": 1 }, "b": { "0.3": 1 } }, "drillDelta": {} }, "pads": { "a": 3, "b": 3, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 7.753891726, "added": 7.601136818 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/MAGIC/BHORIZ", "length": { "a": 102.101815656, "b": 102.101815656, "delta": 0, "perLayer": { "F.Cu": { "a": 20.182107409, "b": 20.511607409, "delta": 0.3295 }, "B.Cu": { "a": 81.919708247, "b": 81.590208247, "delta": -0.3295 } } }, "width": { "min": { "a": 0.4, "b": 0.4 }, "max": { "a": 0.4, "b": 0.4 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 3, "b": 3, "delta": 0, "drills": { "a": { "0.3": 3 }, "b": { "0.3": 3 } }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 5.390130076, "added": 5.389782098 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/MAGIC/BVERT", "length": { "a": 102.757674901, "b": 102.757674901, "delta": 0, "perLayer": { "F.Cu": { "a": 16.439999461, "b": 16.771899461, "delta": 0.3319 }, "B.Cu": { "a": 86.31767544, "b": 85.98577544, "delta": -0.3319 } } }, "width": { "min": { "a": 0.4, "b": 0.4 }, "max": { "a": 0.4, "b": 0.4 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 3, "b": 3, "delta": 0, "drills": { "a": { "0.3": 3 }, "b": { "0.3": 3 } }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 4.209386963, "added": 4.212121856 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/MAGIC/BVIDEO", "length": { "a": 106.171545699, "b": 105.386587186, "delta": -0.784958513, "perLayer": { "B.Cu": { "a": 103.638872244, "b": 102.853913731, "delta": -0.784958513 } } }, "width": { "min": { "a": 0.4, "b": 0.4 }, "max": { "a": 0.4, "b": 0.4 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 1, "b": 1, "delta": 0, "drills": { "a": { "0.3": 1 }, "b": { "0.3": 1 } }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 8.558149795, "added": 7.735459723 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/I2C0_SCL", "length": { "a": 54.946615362, "b": 54.838919836, "delta": -0.107695526, "perLayer": { "F.Cu": { "a": 22.993813276, "b": 22.88611775, "delta": -0.107695526 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 0, "b": 0, "delta": 0, "drills": { "a": {}, "b": {} }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 8.88710188, "added": 8.779406354 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/I2C0_SDA", "length": { "a": 56.759919164, "b": 56.955959928, "delta": 0.196040764, "perLayer": { "F.Cu": { "a": 23.304291117, "b": 23.500331881, "delta": 0.196040764 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 0, "b": 0, "delta": 0, "drills": { "a": {}, "b": {} }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 2.067511543, "added": 2.280660172 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/I2C1_SDA", "length": { "a": 44.602301584, "b": 44.602301584, "delta": 0, "perLayer": {} }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 2, "b": 2, "delta": 0, "drills": { "a": { "0.3": 2 }, "b": { "0.3": 2 } }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 6.058742056, "added": 6.066502805 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/SPI0_RX", "length": { "a": 51.409027571, "b": 52.126614786, "delta": 0.717587215, "perLayer": { "F.Cu": { "a": 46.044765835, "b": 46.224763835, "delta": 0.179998 }, "B.Cu": { "a": 5.364261736, "b": 5.90185095, "delta": 0.537589215 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 1, "b": 1, "delta": 0, "drills": { "a": { "0.3": 1 }, "b": { "0.3": 1 } }, "drillDelta": {} }, "pads": { "a": 3, "b": 3, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 5.266930567, "added": 5.996456744 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/MAGIC/FPGA/SPI0_TX", "length": { "a": 44.068284388, "b": 44.068284388, "delta": 0, "perLayer": {} }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 0, "b": 0, "delta": 0, "drills": { "a": {}, "b": {} }, "drillDelta": {} }, "pads": { "a": 3, "b": 3, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 2.74682338, "added": 2.747037057 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/SPI1_SCK", "length": { "a": 50.714455975, "b": 50.946982259, "delta": 0.232526284, "perLayer": { "F.Cu": { "a": 28.01294645, "b": 27.852839166, "delta": -0.160107284 }, "B.Cu": { "a": 22.701509525, "b": 23.094143092, "delta": 0.392633568 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 3, "b": 3, "delta": 0, "drills": { "a": { "0.3": 3 }, "b": { "0.3": 3 } }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 5.154807021, "added": 5.388715302 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/MAGIC/FPGA/SPI1_TX", "length": { "a": 57.571562131, "b": 57.659835507, "delta": 0.088273376, "perLayer": { "F.Cu": { "a": 43.91445535, "b": 44.239839507, "delta": 0.325384157 }, "B.Cu": { "a": 13.657106781, "b": 13.419996, "delta": -0.237110781 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 2, "b": 2, "delta": 0, "drills": { "a": { "0.3": 2 }, "b": { "0.3": 2 } }, "drillDelta": {} }, "pads": { "a": 5, "b": 5, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 8.591980959, "added": 8.740197091 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/MAGIC/FPGA/SPI1_~{READY}", "length": { "a": 32.805224388, "b": 33.092808877, "delta": 0.287584489, "perLayer": { "F.Cu": { "a": 25.936348623, "b": 26.223933112, "delta": 0.287584489 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 1, "b": 1, "delta": 0, "drills": { "a": { "0.3": 1 }, "b": { "0.3": 1 } }, "drillDelta": {} }, "pads": { "a": 3, "b": 3, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 10.74137808, "added": 11.030993888 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/SYNC", "length": { "a": 83.538746115, "b": 83.538746115, "delta": 0, "perLayer": {} }, "width": { "min": { "a": 0.25, "b": 0.25 }, "max": { "a": 0.25, "b": 0.25 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 2, "b": 2, "delta": 0, "drills": { "a": { "0.3": 2 }, "b": { "0.3": 2 } }, "drillDelta": {} }, "pads": { "a": 3, "b": 3, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 2.985040286, "added": 2.995170423 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/FPGA/~{IRQ}", "length": { "a": 225.882921203, "b": 225.882921203, "delta": 0, "perLayer": {} }, "width": { "min": { "a": 0.25, "b": 0.25 }, "max": { "a": 0.25, "b": 0.25 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 3, "b": 3, "delta": 0, "drills": { "a": { "0.3": 3 }, "b": { "0.3": 3 } }, "drillDelta": {} }, "pads": { "a": 9, "b": 9, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 2.812868405, "added": 2.810678353 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true }, { "name": "/MAGIC/MCU/SD_DETECT", "length": { "a": 19.328303857, "b": 19.328303857, "delta": 0, "perLayer": { "F.Cu": { "a": 6.203413099, "b": 7.158637698, "delta": 0.955224599 }, "B.Cu": { "a": 13.124890758, "b": 12.169666159, "delta": -0.955224599 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 0.2, "b": 0.2 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 2, "b": 2, "delta": 0, "drills": { "a": { "0.3": 2 }, "b": { "0.3": 2 } }, "drillDelta": {} }, "pads": { "a": 2, "b": 2, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 0.899360514, "added": 0.975271429 }, "viasMoved": { "removed": 1, "added": 1 }, "rerouted": true }, { "name": "/POWER/PH", "length": { "a": 20.048321555, "b": 20.048321555, "delta": 0, "perLayer": {} }, "width": { "min": { "a": 0.25, "b": 0.25 }, "max": { "a": 0.25, "b": 0.25 }, "perLayer": {} }, "copperArea": { "a": 63.947644359, "b": 63.14450112, "delta": -0.803143239, "perLayer": { "F.Cu": { "a": 63.947644359, "b": 63.14450112, "delta": -0.803143239 } }, "note": "pour (region) area only" }, "vias": { "a": 0, "b": 0, "delta": 0, "drills": { "a": {}, "b": {} }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 0, "added": 0 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": false }, { "name": "GND", "length": { "a": 2387.88742131, "b": 2396.027875142, "delta": 8.140453832, "perLayer": { "F.Cu": { "a": 1453.208684655, "b": 1457.352313342, "delta": 4.143628687 }, "B.Cu": { "a": 934.678736655, "b": 938.675561799, "delta": 3.996825145 } } }, "width": { "min": { "a": 0.2, "b": 0.2 }, "max": { "a": 1.6, "b": 1.6 }, "perLayer": {} }, "copperArea": { "a": 29430.503408903, "b": 29493.99086091, "delta": 63.487452008, "perLayer": { "F.Cu": { "a": 13801.820387438, "b": 13828.774274181, "delta": 26.953886743 }, "B.Cu": { "a": 15628.683021465, "b": 15665.216586729, "delta": 36.533565264 } }, "note": "pour (region) area only" }, "vias": { "a": 1468, "b": 1562, "delta": 94, "drills": { "a": { "0.3": 1454, "0.8": 14 }, "b": { "0.3": 1548, "0.8": 14 } }, "drillDelta": { "0.3": { "a": 1454, "b": 1548 } } }, "pads": { "a": 263, "b": 266, "added": [ "C111.2", "C112.1", "C113.1", "C12.1" ], "removed": [ "C12.2" ] }, "reroutedLengthMm": { "removed": 69.74688459, "added": 78.021747171 }, "viasMoved": { "removed": 174, "added": 268 }, "rerouted": true }, { "name": "Net-(C81-Pad1)", "length": { "a": 28.146892283, "b": 28.146892283, "delta": 0, "perLayer": {} }, "width": { "min": { "a": 0.25, "b": 0.25 }, "max": { "a": 0.25, "b": 0.25 }, "perLayer": {} }, "copperArea": { "a": 0, "b": 0, "delta": 0, "perLayer": {}, "note": "pour (region) area only" }, "vias": { "a": 0, "b": 0, "delta": 0, "drills": { "a": {}, "b": {} }, "drillDelta": {} }, "pads": { "a": 4, "b": 4, "added": [], "removed": [] }, "reroutedLengthMm": { "removed": 2.022608374, "added": 2.056706781 }, "viasMoved": { "removed": 0, "added": 0 }, "rerouted": true } ] }, "outline": { "changed": false, "loops": { "a": 8, "b": 8 }, "bbox": { "a": [ 91.1125, 93.792, 353.6125, 189.04025 ], "b": [ 91.1125, 93.792, 353.6125, 189.04025 ] }, "size": { "a": [ 262.5, 95.24825 ], "b": [ 262.5, 95.24825 ] }, "perimeterMm": { "a": 567.876702307, "b": 567.876702307, "delta": 0 }, "areaMm2": { "a": 10128.883844019, "b": 10128.883844019, "delta": 0 }, "changedLengthMm": { "removed": 0, "added": 0 } }, "stackup": { "changed": false, "added": [], "removed": [], "modified": [], "reordered": false, "thickness": null }, "warnings": [] }, "bomDiff": { "summary": { "added": 0, "removed": 0, "qtyChanged": 1, "valueChanged": 0, "footprintChanged": 0, "mpnChanged": 0, "dnpToggled": 0, "categoryChanged": 0, "total": 1, "unchanged": 296 }, "added": [], "removed": [], "qtyChanged": [ { "kind": "qty-changed", "category": "SCH", "key": "vf:22u|c_0805_2012metric", "part": { "value": "22u", "footprint": "Capacitor_SMD:C_0805_2012Metric" }, "qtyFrom": 5, "qtyTo": 8, "refsAdded": [ "C111", "C112", "C113" ], "refsRemoved": [], "refs": [ "C7", "C11", "C12", "C15", "C17", "C111", "C112", "C113" ] } ], "valueChanged": [], "footprintChanged": [], "mpnChanged": [], "dnpToggled": [], "categoryChanged": [], "byCategory": { "SCH": { "qtyChanged": 1 }, "PCB": {}, "BOARD_FEATURE": {} } }, "impacts": [ { "id": "900125d728fafca1", "kind": "bom", "ref": "C111", "refs": [ "C111", "C112", "C113" ], "category": "SCH", "metric": "qty", "before": 5, "after": 8, "delta": 3, "severity": "info", "why": "SCH line 22u C_0805_2012Metric: C111, C112, C113 qty changed (qty 5 -> 8).", "causes": [ "bomDiff.qtyChanged[C111]", "bomDiff.qtyChanged[C112]", "bomDiff.qtyChanged[C113]" ], "assumptionDependent": false }, { "id": "98329d175197d5a5", "kind": "impedance", "net": "/IO/GRAPHIC", "layer": "F.Cu", "metric": "z0Ohm", "before": 72.78, "after": 87, "delta": 14.22, "severity": "info", "why": "/IO/GRAPHIC: rerouted (37.87 mm new copper); F.Cu width 0.4 -> 0.25-0.4 mm - Z0 on F.Cu 72.78 ohm -> 87 ohm (+14.22), with no limit to judge against.", "causes": [ "layoutDiff.nets.changed[/IO/GRAPHIC]" ], "assumptionDependent": true } ], "summary": { "counts": { "high": 0, "medium": 0, "low": 0, "info": 2 }, "headline": "2 informational change(s), none against a limit; first: SCH line 22u C_0805_2012Metric: C111, C112, C113 qty changed (qty 5 -> 8).", "markdown": "**2 informational change(s), none against a limit; first: SCH line 22u C_0805_2012Metric: C111, C112, C113 qty changed (qty 5 -> 8).** Layout: components: 3 added, 2 moved, 1 rotated; nets: 1 changed, 60 rerouted. BOM: 1 changed quantity. Re-analysed on both revisions, for the changed nets and parts only: impedance, cert. Every electrical change is informational (improved, or no limit to judge against). Not run for missing inputs: cert.creepage, returnPath (see refused). Rows marked assumptionDependent rest on ledgered typical values." }, "analysed": { "ran": [ "impedance", "cert" ], "nets": [ "+1V2", "+3V3", "+5V", "+9V_Unreg", "/CASS/CASS2_READ", "/CASS/CASS_A_READ", "/CASS/CASS_A_~{SWITCH}", "/CPU \\ RAM/A0", "/CPU \\ RAM/A1", "/CPU \\ RAM/A2", "/CPU \\ RAM/D0", "/CPU \\ RAM/D4", "/CPU \\ RAM/D5", "/CPU \\ RAM/~{ML}", "/CPU \\ RAM/~{NMI}", "/CPU \\ RAM/~{RES}", "/CPU \\ RAM/~{VP}", "/IEEE/ATN", "/IEEE/ATN_OUT", "/IEEE/DAV", "/IEEE/DAV_OUT", "/IEEE/DIO1", "/IEEE/DIO3", "/IEEE/DIO4", "/IEEE/DIO5", "/IEEE/DIO6", "/IEEE/DIO7", "/IEEE/DIO_IN8", "/IEEE/DIO_OUT8", "/IEEE/EOI", "/IEEE/EOI_IN", "/IEEE/EOI_OUT", "/IEEE/IFC", "/IEEE/IFC_OUT", "/IEEE/NDAC", "/IEEE/NDAC_IN", "/IEEE/NRFD", "/IEEE/SRQ", "/IO/BD0", "/IO/DIAG", "/IO/GRAPHIC", "/IO/VIA_CA1", "/IO/VIA_CB2", "/IO/VIA_PA2", "/MAGIC/BHORIZ", "/MAGIC/BVERT", "/MAGIC/BVIDEO", "/MAGIC/FPGA/I2C0_SCL", "/MAGIC/FPGA/I2C0_SDA", "/MAGIC/FPGA/I2C1_SDA", "/MAGIC/FPGA/SPI0_RX", "/MAGIC/FPGA/SPI0_TX", "/MAGIC/FPGA/SPI1_SCK", "/MAGIC/FPGA/SPI1_TX", "/MAGIC/FPGA/SPI1_~{READY}", "/MAGIC/FPGA/SYNC", "/MAGIC/FPGA/~{IRQ}", "/MAGIC/MCU/SD_DETECT", "/POWER/PH", "GND", "Net-(C81-Pad1)" ], "rails": [] }, "assumptions": { "before": [ { "source": "default", "analysis": "impedance", "key": "mask.er", "value": 3.8, "citation": "LPI solder mask epsilon_r 3.8 (NativeCAD default)", "verified": false, "affects": [ "outer-layer traces" ] }, { "source": "default", "analysis": "cert", "key": "fab", "value": "jlcpcb", "citation": "fab profile jlcpcb (NativeCAD default)", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "ipc6012.drillPositionTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.innerRegistrationTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.outerRegistrationTolMm", "value": 0.05, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipcClass", "value": "2", "citation": "IPC-6012 Class 2 (dedicated service) - the general commercial default", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "motC", "value": 105, "citation": "requested MOT 105 C (FR-4 laminates' common UL RTI)", "verified": false, "affects": [], "unit": "C" }, { "source": "default", "analysis": "returnPath", "key": "erEff", "value": 4, "citation": "effective epsilon_r 4 for the stitching distance (NativeCAD default)", "verified": false, "affects": [] }, { "source": "derived", "analysis": "returnPath", "key": "planes", "value": [], "citation": "inner layer with >= 30 % pour cover of one net (outer: >= 80 % and no other net's traces); voids = holes >= 2 mm^2 in that net's pours, as bounding rectangles", "affects": [ "every finding" ] }, { "source": "default", "analysis": "returnPath", "key": "riseTimeNs", "value": 1, "citation": "edge rise time 1 ns, f_knee = 0.35 / t_r (Johnson & Graham)", "verified": true, "affects": [], "unit": "ns" } ], "after": [ { "source": "default", "analysis": "impedance", "key": "mask.er", "value": 3.8, "citation": "LPI solder mask epsilon_r 3.8 (NativeCAD default)", "verified": false, "affects": [ "outer-layer traces" ] }, { "source": "default", "analysis": "cert", "key": "fab", "value": "jlcpcb", "citation": "fab profile jlcpcb (NativeCAD default)", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "ipc6012.drillPositionTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.innerRegistrationTolMm", "value": 0.075, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipc6012.outerRegistrationTolMm", "value": 0.05, "unit": "mm", "citation": "NativeCAD default (typical standard-technology rigid fab; no fab publishes it)", "verified": false, "affects": [ "ipc6012" ] }, { "source": "default", "analysis": "cert", "key": "ipcClass", "value": "2", "citation": "IPC-6012 Class 2 (dedicated service) - the general commercial default", "verified": true, "affects": [] }, { "source": "default", "analysis": "cert", "key": "motC", "value": 105, "citation": "requested MOT 105 C (FR-4 laminates' common UL RTI)", "verified": false, "affects": [], "unit": "C" }, { "source": "default", "analysis": "returnPath", "key": "erEff", "value": 4, "citation": "effective epsilon_r 4 for the stitching distance (NativeCAD default)", "verified": false, "affects": [] }, { "source": "derived", "analysis": "returnPath", "key": "planes", "value": [], "citation": "inner layer with >= 30 % pour cover of one net (outer: >= 80 % and no other net's traces); voids = holes >= 2 mm^2 in that net's pours, as bounding rectangles", "affects": [ "every finding" ] }, { "source": "default", "analysis": "returnPath", "key": "riseTimeNs", "value": 1, "citation": "edge rise time 1 ns, f_knee = 0.35 / t_r (Johnson & Graham)", "verified": true, "affects": [], "unit": "ns" } ] }, "refused": { "before": [ { "analysis": "cert.creepage", "reasonCode": "pcb_analysis_needs_input", "needs": [ "cert.pairs[].a", "cert.pairs[].b", "cert.pairs[].workingVrms" ], "remedy": "creepage needs the net pairs and the working voltage between them; UL 796 and IPC-6012 ran without them", "requested": false }, { "analysis": "returnPath", "reasonCode": "pcb_analysis_needs_input", "needs": [ "a reference plane (a poured copper layer)" ], "remedy": "no layer of this board is a plane, so there is no return path to check", "requested": false } ], "after": [ { "analysis": "cert.creepage", "reasonCode": "pcb_analysis_needs_input", "needs": [ "cert.pairs[].a", "cert.pairs[].b", "cert.pairs[].workingVrms" ], "remedy": "creepage needs the net pairs and the working voltage between them; UL 796 and IPC-6012 ran without them", "requested": false }, { "analysis": "returnPath", "reasonCode": "pcb_analysis_needs_input", "needs": [ "a reference plane (a poured copper layer)" ], "remedy": "no layer of this board is a plane, so there is no return path to check", "requested": false } ] } } }