Your board, analysed before it is built.

• ULX3S on JLCPCB meets the fab's UL-recognized construction (UL 796 design check).
• ULX3S is IPC-6012 Class 2 ready (100% via ring retention under the fab's drill tolerance).

Design checks against the standards, not certificates issued by their bodies. Each line is a shipped entry in our standards claims register.

Pick a copper layer, drag to pan, wheel or pinch to zoom, hover for V, |J| and T. Switch to 3D for the stackup, click a red cut marker for the trace cross-section. Full-screen viewer

Power on a real FPGA board

The ULX3S is an open-hardware Lattice ECP5 board. Every copper pour, trace and via on its 3.3 V and 1.1 V rails comes from the board file, the regulator feeds each rail and the chips draw their load. The 3.3 V rail drops 3.58 mV at its farthest load, 2.2% of the ±5% window.

One change, before and after

All of the 3.3 V current climbs through a single via into the inner plane. Two more vias beside it cut the worst drop from 3.58 mV to 3.33 mV (7.1% lower) and the busiest via from 0.48 A to 0.25 A.

Impedance of the core rail, 10 kHz to 1 GHz

Seen from the ECP5's core vias, the 1.1 V rail stays under its 0.37 Ω target (±5% of nominal over a 0.15 A load step) up to 141 MHz. Above that the loops that mount its 3 caps take over: each via pair adds 0.71 nH. Adding one 0402 1 µF X5R cap on the core vias holds the rail under target to 200 MHz and cuts the impedance at 100 MHz from 0.26 Ω to 0.19 Ω, 27% lower.

Impedance, straight from the board file

The Antmicro Signal Integrity Test Board is open hardware. Antmicro designs its single lines 0.2 mm wide for 50 Ω; our solve of the board's stackup at that width gives 50.6 Ω. As drawn in the board file, 0.185 mm wide, the PASS line solves to 52.7 Ω, inside the ±10 % a controlled-impedance order allows.

Open the Antmicro board in the viewer above and pick Z0 to see every trace coloured by its impedance.

Impedance yield across the fab's tolerances

All 2,000 simulated builds of a 0.15 mm microstrip land within ±10 % of its 55.54 Ω nominal, and 99.75% within ±7 %. The differential pair at a 0.2 mm gap does the same: all 1,000 builds within ±10 % of 99.02 Ω, 99.80% within ±7 %. Trace width moves impedance most, then dielectric height; etch factor barely registers.

What moves impedance

Each parameter pushed to the edge of its spread with everything else at nominal; the bar shows how far the impedance goes.

Glass weave skew, from the real cell

Rotate the route a few degrees off the weave and the skew drops to 0.09 to 0.35 ps/in across four glass styles, in line with the 0.2 ps/in Samtec measured on rotated routes: 20–40× less than along the grain.

Along the grain, skew swings sinusoidally with where the pair sits on the glass. At the worst position it reaches 7.6 ps/in on 1078: the perfectly aligned upper bound, since a real route wanders off the grain. Measured worst cases sit under it; the bound is 2.3×, 1.5× and 1.6× the worst Samtec (Megtron 6) and Isola (I-Speed) published for 1035, 1078 and 3313.

Worst-case skew in ps/in. Along grain: the model's worst position; published: the measured worst case and its laminate; ratio: along grain / published.

Eye diagrams at 25 and 56 Gbps

Eye open at 1e-12. The Antmicro PASS line at 56 Gbps NRZ keeps 1.02 V by 13.7 ps at BER 1e-12 as drawn, and 1.27 V by 14.7 ps with Tx FFE, CTLE and a 2-tap DFE optimised for that BER.

Back-drill buys 1,726 mV of eye height at 56 Gbps. Solved channel responses of the Antmicro PASS line (45.4 mm) and DIFF pair (55.4 mm) at their board-file geometry, and the same cross-sections at twice the length. Switch data rate, surface roughness, equalisation, pair skew and the via (none, with via, back-drilled); the marker sits at the widest opening. Coloured contours are the statistical eye at BER 1e-6 to 1e-15; the strip below is its bathtub.

Impedance along the line

The TDR view, from S-parameters. Reflection data is extrapolated to DC, windowed and inverse-transformed into a step response, then read as impedance against distance for the rise time you pick. The Antmicro stub_short board is shown twice through the same pipeline: the measured VNA reflection and our line-only model. The model has no SMA launch, stub or fixture, so the measured launch dip and the later bump have no counterpart in it, and its level sits a few ohms above the measured trace. Other cases: a uniform line, a higher-impedance section, and a differential via.

Via life before you drill

An 8-layer, 1.6 mm board with a 0.25 mm plated-through hole cycling 25 to 150 °C: the barrel stays elastic, at 243 MPa by IPC-TR-579 against copper's 250 MPa yield, and the IPC-TR-579 fatigue equation gives it 820,000 cycles. Lead-free reflow is where the barrel works hard: 113 excursions to 260 °C to failure, so six reflows use 5.3% of its life.

820,000cycles, 25 to 150 °C

113reflow excursions to failure at 260 °C

5.3%of barrel life used by six lead-free reflows

The resolved model of the same cell puts mid-barrel strain at 0.23%, peaking at 196 MPa in the barrel.

Survives the shaker

A 273 Hz first mode for the 160 by 100 mm, 1.6 mm board with five parts loaded on it (Rayleigh-Ritz, simply-supported sin basis, lumped component point masses). On a 8.9 g rms random profile the board centre moves 0.253 mm at three sigma, and the Steinberg criterion for a 20-million-cycle life leaves every part with margin. The drop is tighter: a 1,500 g, 0.5 ms half-sine (JESD22-B111 condition B) puts 3,491 µε of peak strain at the BGA against a 1,500 µε limit.

Margin is allowable divided by demand; under 1.0 fails. Drop margin is the 1,500 µε strain limit divided by the peak strain at the part.

Matches the fabs

11 of 17 published fab geometries (65%) land within ±2% of the fab's own number; all 17 are within ±5%, worst 4.9%, and nothing is fitted. Each row is a stackup and trace width that a fab publishes, solved as drawn with a rectangular trace and the fab's printed Dk.

Return-path check

Pre-compliance screen: 1 return-path finding before stitching, 0 after. A clock trace with a 0 MHz knee crosses a split in its ground plane on a four-layer synthetic board. One stitching capacitor within 21.4 mm of the crossing gives the return current a path and clears the finding. The radiated figures below are closed-form pre-compliance estimates, not a compliance test; only measurement in an accredited chamber shows compliance.

Trace current capacity

10 of 13 published trace-current cases land within 15% of the open reference, the best of them within 12.5%. Outer and inner layers, with and without a back plane, two copper weights, all at a 20 K rise. The reference is Adam 2007 (Haus der Technik), an open paper with its own simulations and correlation. The misses are the narrowest traces, where we carry slightly more current than the paper, and the grid is converged there.

Limits used below: 68.3 A/mm² outer, 34.2 A/mm² inner, at a 10 K rise. A 0.3 mm drill via with 25 µm plating has 0.026 mm² of barrel and carries 0.95 A at that rise.

Channel COM, checked against the reference

7 of 7 channels agree with the IEEE 802.3 reference implementation to under 0.001 dB, far inside the ±0.1 dB correlation window. Every channel clears the 3 dB Channel Operating Margin limit, from a 100 mm trace to a 1000 mm route with vias and three crosstalk aggressors.

Get this breakdown for your board

Bring KiCad, Gerber or IPC-2581. NativeCAD gives you IR drop and current on every rail, impedance on every controlled trace, weave skew on your glass, eyes on your fastest links and life on every via, before the first panel is built.